This article describes the procedure to Configure and program EXAR Corporation’s PowerXR Digital Power devicesvia I2C interface. Details shown here apply to XRP7704/08/40 and XRP7713/14 devices and PowerArchitectsoftware version 3.00.
上传时间： 2013-10-20
上传用户：tianyi223
CodeWarrior Development Tool Suites are comprehensive integrated developmentenvironments (IDE) that provide a highly visual and automated framework toaccelerate the development of the most complex embedded applications. Acrossmost stages of the development cycle, we offer tools to help Configure, debug andoptimize your design built on Freescale MPUs, MCUs, DSPs and DSCs. These toolsuites provide solutions to get your design up and running fast.
标签： CodeWarrior 开发工具套件
上传时间： 2013-11-07
上传用户：youlongjian0
The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and Configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
上传时间： 2013-10-26
上传用户：agent
Nios II 系列处理器配置选项:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can Configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.
上传时间： 2015-01-01
上传用户：mahone
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to Configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be Configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to ConfigureVirtex-5 RocketIO™ GTP transceivers• Users can Configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically Configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-20
上传用户：dave520l
sheerdns is a master DNS server whose zone records are stored on a One-Record-Per-File bases. Because of this, it is the simplest of any DNS to Configure, the easiest to update, and the most efficient for networks that experience a lot of updates (for example master servers for dynamic IP address ranges). You never have to restart it; any updates are available immediately without having to notify the sheerdns process. 来源: http://freshmeat.net/projects/sheerdns/?topic_id=149 sheerdns是一个主DNS服务器，它的域记录保存在一个One-Record-Per-File（每文件一个记录）的库中。因此，它是最简单的DNS配制，最容易更新，对于有大量更新的网络（如动态IP地址范围的主服务器）来说它是最高效的。你不必重新启动它，任何更新不用通知对应DNS进程就可以立即生效。
标签： One-Record-Per-File sheerdns records Becaus
上传时间： 2015-01-10
上传用户：wyc199288
gcj java applet的web browser 插件，可替代jre 安装步骤: ./Configure make make install
上传时间： 2014-12-02
上传用户：redmoons
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to Configure and connect the IP cores without the need to modify any global resources.
标签： system-on-chip integrated designed reusable
上传时间： 2013-12-20
上传用户：小眼睛LSL
如果已经安装好了vobsub，就可以运用vobsub里面带的字幕提取工具vsrip提取字幕。 打开VobSub程序组,运行vobsub.Configure,点击Open来打开vts_01_0.ifo文件(此文件已经拷贝到硬盘上,无需从光盘上找),选定放置字幕文件的子目录,点击确定.提取完成之后会生成Vts_01_0.sub和vts_01_0.idx两个字幕文件,若按照DVDrip的做法是在最终视频文件生成之后,将字幕文件更名并与主体一致,但在此这个步骤被提前了,因为real格式文件的字幕是嵌入在画面那的.我们需要做的是将vts_01_0.idx和vts_01_0.sub更名为vts_01_1.idx和vts_01_1.sub,与vts_01_1.vob同名.这样才能进行制作时被vobsub自动调用同步嵌入字幕
标签： vobsub
上传时间： 2015-04-28
上传用户：wangdean1101
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already Configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you Configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
标签： the Analyzer Compiler project
上传时间： 2013-12-19
上传用户：Yukiseop
