Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate mo...
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Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate mo...
verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y
ST7920 LCD driver source code, which include the LCD init and output the string to LCD.
verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remai...
Features: High efficiency, high reliability, low cost AC input range selected by switch 100% ful...
The power supply shown in Figure 1 is implemented using a simplebuck topology that allows for tw
computes Input/output auto/cross-correlation.