编写testbench的超好教程
编写testbench的超好教程，网上这种资料比较少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf...
Co-Verification技术资料
📦 资源总数：180
📄 技术文档：1
💻 源代码：119415
🔌 电路图：1
📚 Co-Verification全部资料 (180个)
The package contains a Reed-Solomon coding and decoding program, derived partly from Phil Karn/Rob
The package contains a Reed-Solomon coding and decoding program, derived partly from Phil Karn/Rob...
dephi OBD II 技术路线,所谓OBD-II是一个系列的法规
dephi OBD II 技术路线,所谓OBD-II是一个系列的法规，目的是通过检测整个动力总成系统的故障或劣化来减少在用车的排放，排放控制系统是OBD-II的基础。OBD-II同时也提供诊断的标准化...
此软件功能强大 It operates in the highly ompetitive UK banking sector against ...barcode reader to reduce h
此软件功能强大 It operates in the highly ompetitive UK banking sector against ...barcode reader to reduce h...
Neural network match filter of chirp pulse compression Neural network match filter of chirp pulse co
Neural network match filter of chirp pulse compression Neural network match filter of chirp pulse co...
Atmel’s AT91SAM7FP105 is a low pincount FingerChip processor based on the 32-bit ARM RISC processor
Atmel’s AT91SAM7FP105 is a low pincount FingerChip processor based on the 32-bit ARM RISC processor...
This a very simple baseband simulator for SC-FDMA system. This simulator is part of the upcoming boo
This a very simple baseband simulator for SC-FDMA system. This simulator is part of the upcoming boo...
In the previous article, we presented an approach for capturing similarity between words that was co
In the previous article, we presented an approach for capturing similarity between words that was co...
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation ...
A code writing by Verilog which can find medium value. With a C file to see the simulation results.
A code writing by Verilog which can find medium value. With a C file to see the simulation results. ...