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模拟电子 数字集成电路设计Digital Integrated Circuit Design
 
This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Coverin ...
模拟电子 逐次逼近式AD转换器研究
A tutorial on SAR type A/D converters, this note contains detailed information on several 12-bit circuits. Comparator, clocking, and preamplifier designs are discussed. A final circuit gives a 12-bit conversion in 1.8µs. Appended sections explain the basic SAR technique and explore D/A consi ...
单片机编程 Clocking Options for Stellaris
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after t ...
单片机编程 用单片机配置FPGA—PLD设计技巧
用单片机配置FPGA—PLD设计技巧
Configuration/Program Method for Altera Device
Configure the FLEX Device
You can use any Micro-Controller to configure the FLEX device–the main idea is clocking in ONE BITof configuration data per CLOCK–start from the BIT 0􀂄The total Configuration time–e.g. ...
教程资料 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
 
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
通信网络 带有SerDes接口的PLB千兆位级以太网MAC
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserial ...
可编程逻辑 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
 
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
DSP工具/软件 tas3204
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio™ suite of DS ...
笔记 Vivado时序约束
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. SDC has been in use and evolving for more than 20 years, making it the most popular and pr ...
技术资料 vivado集成开发环境时序约束介绍
本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变就是约束文件，5E软件支持的是UcF（User Constraints file，而 Vivado软件转换到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Design Constraints）标准 ...