搜索：Clock+Divider

找到约 426 项符合「Clock+Divider」的查询结果

结果 426
热门搜索： STM32 FPGA PCB设计 电路图 51单片机 嵌入式 Arduino MATLAB Verilog Python
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https://www.eeworm.com/dl/692/467010.html 行业发展研究

DDS divider clock AHDL

DDS divider clock AHDL
下载 32
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查看 1061
https://www.eeworm.com/dl/663/311790.html VHDL/FPGA/Verilog

VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..

VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
下载 29
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查看 1116
https://www.eeworm.com/dl/628/438851.html 编译器/解释器

multiplier and divider verilog codes

multiplier and divider verilog codes
下载 71
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查看 1027
https://www.eeworm.com/dl/534/483744.html 其他

this file is divider vhdl program

this file is divider vhdl program
下载 157
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查看 1041
https://www.eeworm.com/dl/663/413318.html VHDL/FPGA/Verilog

a divider design based on verilog language

a divider design based on verilog language
下载 108
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查看 1067
https://www.eeworm.com/dl/534/457922.html 其他

program to perform sequential divider in vhdl

program to perform sequential divider in vhdl
下载 48
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查看 1043
https://www.eeworm.com/dl/910946.html 技术资料

Clock

Clock VHDL !!!!!!!!!
下载 3
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查看 2477
https://www.eeworm.com/dl/966101.html 技术资料

CLOCK

32位微型计算机 电子时钟汇编程序，在屏幕上显示时分秒，
下载 5
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查看 2372
https://www.eeworm.com/dl/663/488484.html VHDL/FPGA/Verilog

It is n-bit sequential divider in verilog language

It is n-bit sequential divider in verilog language
下载 110
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查看 1111
https://www.eeworm.com/dl/973561.html 技术资料

msp430+clock

用msp430单片机实现时钟，考虑到低功耗编程。
下载 9
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查看 5608