特点 精确度0.05%满刻度 ±1位数 显示范围-19999-99999可任意规划 可直接量測直流4至20mA電流,無需另接輔助電源 尺寸小(24x48x50mm),穩定性高 分离式端子,配线容易 CE 认证 主要規格 辅助电源: None 精确度: 0.05% F.S. ±1 digit(DC) 输入抗阻: approx. 250 ohm with 20mA input 输入电压降: max. DC5V with 20mA input 最大过载能力: < ±50mA 取样时间: 2.5 cycles/sec. 显示值范围: -19999 - 99999 digit adjustable 归零调整范围: -999-999 digit adjustable 最大值调整范围: -999-999 digit adjustable 过载显示: " doFL " or "-doFL" 极性显示: " 一 " for negative readings 显示幕 : Brigh Red LEDs high 8.6mm(.338") 温度系数 : 50ppm/℃ (0-50℃) 参数设定方式: Touch switches 记忆型式: Non-volatile E2 外壳材料: ABS 绝缘耐压能力: 2KVac/1 min. (input/case) 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) 外型尺寸: 24x48x50mm CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
Class="time">上传时间： 2013-10-09
Class="username">上传用户：lhuqi
特点 精确度0.1%满刻度 ±1位数 显示范围-19999-99999可任意规划 可直接量测直流电流/直流电压,无需另接辅助电源 尺寸小(24x48x50mm),稳定性高 分离式端子,配线容易 CE 认证 2.主要規格 辅助电源: None 精确度: 0.1% F.S. ±1 digit(1-100%F.S.) 输入抗阻 : >100Mohm(<2V range) >2Mohm(<2Vrange) < 0.25VA(current ranges) < 1000Vrms(>54V ranges) 最大过载能力: < 150Vrms(<54V ranges)
Class="time">上传时间： 2013-10-08
Class="username">上传用户：tiantwo
6小时学会labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in Class, you can choose whether to assign the exercises as homework or to be done in Class. If you decide to assign the exercises in Class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
Class="tags">标签： labview
Class="time">上传时间： 2013-10-13
Class="username">上传用户：zjwangyichao
解压包包含了C语言入门经典教程和Visuak c++软件 【基本简介】 Visual C++是一个功能强大的可视化软件开发工具。自1993年Microsoft公司推出Visual C++1.0后，随着其新版本的不断问世，Visual C++已成为专业程序员进行软件开发的首选工具。 虽然微软公司推出了Visual C++.NET(Visual C++7.0)，但它的应用的很大的局限性，只适用于Windows 2000,Windows XP和Windows NT4.0。所以实际中，更多的是以Visual C++6.0为平台。 Visual C++6.0不仅是一个C++编译器，而且是一个基于Windows操作系统的可视化集成开发环境（integrated development environment,IDE）。Visual C++6.0由许多组件组成，包括编辑器、调试器以及程序向导AppWizard、类向导Class Wizard等开发工具。 这些组件通过一个名为Developer Studio的组件集成为和谐的开发环境。 在Visual C++ 6.0 企业版的基础上集成官方的SP6升级补丁制作而成！免序列号，安装完即可使用，无需再打补丁！ 【使用方法】 有些朋友反应在安装后出现 "Error spawning error" 可以看看下面绿色软件找到的一些解决方案： 点击VC“TOOLS（工具）”—>“Option（选择）”—>“Directories（目录）”重新设置“Excutable Fils、Include Files、Library Files、Source Files”的路径。很多情况可能就一个盘符的不同（例如你的VC装在C，但是这些路径全部在D），改过来就OK了。
Class="time">上传时间： 2013-10-09
Class="username">上传用户：hui626493
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-Class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
Class="tags">标签： UltraScale Xilinx 架构
Class="time">上传时间： 2013-11-21
Class="username">上传用户：wxqman
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new Class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
Class="tags">标签： xilinx Zynq 7000 EPP
Class="time">上传时间： 2013-10-09
Class="username">上传用户：evil
微电脑型RS-485显示电表（24*48mm/48*96mm） 特点： 5位数RS-485显示电表 显示范围-19999-99999位數 通訊协议Modbus RTU模式 宽范围交直流兩用電源設計 尺寸小,穩定性高 主要规格： 显示范围:-19999~99999 digit RS-485传输速度: 19200/9600/4800/2400 selective RS-485通讯位址: "01"-"FF" RS-485通讯协议: Modbus RTU mode 显示幕: Red high efficiency LEDs high 10.16 mm (0.4") (MMX-RS-11X) Red high efficiency LEDs high 20.32 mm (0.8") (MMX-RS-12X) Red high efficiency LEDs high 10.16 mm (0.4")x2 (MMX-RS-22X) 参数设定方式: Touch switches 记忆方式: Non-volatile E²PROM memory 绝缘耐压能力: 2KVac/1 min. (input/power) 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
Class="time">上传时间： 2015-01-03
Class="username">上传用户：feitian920
微电脑型单相交流集合式电表（单相二线系统） 特点： 精确度0.25%满刻度±1位数 可同时量测与显示交流电压,電流,頻率,瓦特,(功率因數/視在功率) 交流電壓,電流,瓦特皆為真正有效值(TRMS) 交流電流,瓦特之小數點可任意設定 瓦特單位W或KW可任意設定 CT比可任意設定(1至999) 輸入與輸出絕緣耐压 2仟伏特/1分鐘( 突波測試強度4仟伏特(1.2x50us) 數位RS-485界面 (Optional) 主要规格： 精确度: 0.1% F.S.±1 digit (Frequency) 0.25% F.S.±1 digit(ACA,ACV,Watt,VA) 0.25% F.S. ±0.25o(Power Factor) (-.300~+.300) 输入负载: <0.2VA (Voltage) <0.2VA (Current) 最大过载能力: Current related input: 3 x rated continuous 10 x rated 30 sec. 25 x rated 3sec. 50 x rated 1sec. Voltage related input: maximum 2 x rated continuous 过载显示: "doFL" 显示值范围: 0~600.0V(Voltage) 0~999.9Hz(Frequency)(<20% for voltage input) 0~19999 digit adjustable(Current,Watt,VA) 取样时间: 2 cycles/sec. RS-485通讯位址: "01"-"FF" RS-485传输速度: 19200/9600/4800/2400 selective RS-485通信协议: Modbus RTU mode 温度系数: 100ppm/℃ (0-50℃) 显示幕: Red high efficiency LEDs high 10.16 mm(0.4") 参数设定方式: Touch switches 记忆型式: Non-volatile E²PROM memory 绝缘抗阻: >100Mohm with 500V DC 绝缘耐压能力: 2KVac/1 min. (input/output/power) 1600 Vdc (input/output) 突波测试: ANSI c37.90a/1974,DIN-IEC 255-4 impulse voltage 4KV(1.2x50us) 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
Class="tags">标签： 微电脑 单相交流 单相 电表
Class="time">上传时间： 2015-01-03
Class="username">上传用户：几何公差
集合式直流电能表（小功率的） 特点： 精确度0.05%满刻度±1位数 可同时量测与显示/直流电压/电流/瓦特（千瓦）/瓦特小时（千瓦小时） 电压输入（DC0-99.99V/0-600.0V）自动变档功能 显示范围0-9999(电流/瓦特/千瓦),0至99999999(八位數瓦特小时)可任意规划 数位RS-485 界面 (Optional) 主要规格： 辅助电源消耗功率：＜0.35VA(DC12V/DC24V) ＜0.5VA（DC48V） ＜1.5VA（AC90-240V(50/60Hz)） 精确度: 0.05% F.S. ±1 digit (23 ±5℃) 输入范围：Auto range(DC0-99.99V/0-600.0V(DC voltage)) 输入抗阻：＞5MΩ（DC voltage） 取样时间：10 cycles/second(total) 过载显示: " doFL " 显示值范围: 0-9999 digit（DCA/W(KW)） 0-9999999.999 digit(WH/(KWH)) RS-485传输速度: 19200/9600/4800/2400 selective RS-485通讯位址: "01"-"FF"（0-255） RS-485通信协议: Modbus RTU mode 温度系数: 50ppm/℃ (0-50℃) 显示幕:Bight Red LEDs high 10.16 mm(0.4") 参数设定方式: Touch switches 记忆方式: Non-volatile E²PROM memory 绝缘耐压能力:2KVac/1min.(input/output)（RS-485(Isolating)） 1600 Vdc (input/output) （RS-485(Isolating)） 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
Class="time">上传时间： 2013-11-20
Class="username">上传用户：s363994250
This article is based in part on Bob Place s ADO is AOK (a simple ADO tutorial). Wrapper Usage This is consist of 2 Classes. CDyndb : This Class manages connections and recordsets. Recordsets are organized as linked list (CList) and you can access them using their ids. CDynRec : This Class is the node to populate for each recordsets. ADO封装器类 这篇文章一部分基于Bob Place的《ADO is AOK》 (简单的ADO指导) 。 包裹的用法 由2个类组成。 类CDyndb: 这个类别管理连接和记录集。记录集是连接起来的记录的集合，你可以通过他们的ID访问他们。 类CDynRec: 这个类别存放记录集的代码。
Class="tags">标签： This ADO tutorial article
Class="time">上传时间： 2013-12-14
Class="username">上传用户：wfl_yy
