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模拟电子 基于Contourlet域HMT模型的Cycle Spinning去噪方法
为了提高图像去噪效果，提出了基于Contourlet域HMT模型的Cycle Spinning去噪方法。首先将待去噪图像进行循环平移，使用Contourlet域HMT模型对平移后的图像进行降噪处理，然后将降噪后的图像进行循环反平移，最后将不同循环平移量下的降噪图像进行平均处理，以减少去噪后图像的失真。实验结果表明，该方法不仅可以提高降噪后 ...
Java编程 Cycle slip probability of the phase unrapping algorithm
Cycle slip probability of the phase unrapping algorithm
软件设计/软件工程 IEEE软件生命周期过程管理标准 IEEE Standard for Information Technology - Software Life Cycle
IEEE软件生命周期过程管理标准
IEEE Standard for Information Technology - Software Life Cycle
其他 ADSP-BF535 Blackfin® Processor Multi-cycle Instructions and Latencies
ADSP-BF535 Blackfin® Processor Multi-cycle Instructions and Latencies
其他嵌入式/单片机内容 show 0-F cycle by cycle in ARM7
show 0-F cycle by cycle in ARM7
DSP编程 This demo shows the use of the PWM block in generating the pulse waveform whose duty cycle is changi
This demo shows the use of the PWM block in generating the pulse waveform whose duty cycle is changing regularly. The PWM waveform period is variable, while the width of the pulse remains constant.
VHDL/FPGA/Verilog VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
加密解密 CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b
CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset
VHDL/FPGA/Verilog Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, sp
Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
其他 Write a program to decide if a graph has a cycle or not. The given graph can be a directed or undire
Write a program to decide if a graph has a cycle or not. The given graph can be a directed or undirected graph, which is indicated at the time of reading the input (0 for directed graph and 1 for undirected graphs). The input is given as an adjacency list.