CPU+Simulation
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1,604
CPU+Simulation 全部资料 1,604 份
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static c...
2014-12-20
116
Verilog-RISC CPU 代码 实现了简单的RISC cpu
Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航
2016-12-25
86
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is wr
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static cha...
2014-11-09
183
his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is w
his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static ch...
2013-12-23
150