随着对高功率因数的变换器的需求不断增长，功率因数为1（unity power factor）的电源供给越来越受到欢迎。在计算机或其它一些设备上，电源要求鲁棒性好、可靠、抗干扰能力强。而数字控制正提供了这方面的保障。
上传时间： 2021-12-12
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数字化电源的特点：1.控制智能化它是以数字信号处理器(DSP)或微控制器(MCU)为核心，将数字电源驱动器及PWM控制器作为控制对象而构成的智能化开关电源系统。传统的由微控制器控制的开关电源，一般只是控制电源的启动和关断，并非真正意义的数字电源。2.数模组件组合优化采用“整合数字电源”(Fusion Digital Power)技术，实现了开关电源中模拟组件与数字组件的优化组合。例如，功率级所用的模拟组件MOSFET驱动器，可以很方便地与数字电源控制器相连并实现各种保护及偏置电源管理，而PWM控制器也属于数控模拟芯片。3.集成度高实现了电源系统单片集成化(Power System on Chip)，将大量的分立式元器件整合到一个芯片或一组芯片中。4.控制精度高能充分发挥数字信号处理器及微控制器的优势，使所设计的数字电源达到高技术指标。例如，其脉宽调制(PWM)分辨力可达150ps(10~12s)的水平，这是传统开关电源所望尘莫及的。数字电源还能实现多相位控制、非线性控制、负载均流以及故障预测等功能，为研制绿色节能型开关电源提供了便利条件。5.模块化程度高数字电源模块化程度高，各模块之间可以方便地实现有机融合，便于构成分布式数字电源系统，提高电源系统的可靠性。
标签： 全数字电源
上传时间： 2021-12-13
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This Section covers the design of power transformers used in buck-derived topologies: forward converter, bridge, half-bridge, and full-wave centertap. Flyback transformers (actually coupled inductors) are covered in a later Section. For more specialized applications, the principles discussed herein will generally apply.
上传时间： 2021-12-16
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隔离+非隔离双路12V转5V DCDC电源模块ALTIUM设计硬件原理图+PCB+AD集成封装库文件，2层板设计，大小为54x35mm，Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，已制样板测试验证，可作为你产品设计的参考。集成封器件型号列表：Library Component Count : 13Name Description----------------------------------------------------------------------------------------------------0402 100nF (104) 10% 16V贴片电容0402 10KΩ (1002) 1%贴片电阻0402 1KΩ (1001) 1% 贴片电阻0402 5.1KΩ (5101) 1%贴片电阻0603 红灯 发光二极管0603 绿灯 发光二极管0805 22uF (226) 20% 25V贴片电容0805 白灯 发光二极管DC-DC 12V-5V 隔离DC-DC 12V-5VHT396R-2P 弯针电源接口PH2.0 14PPOWER SOURCE 电源接口SOT-223 AMS1117-5.0 低压差线性稳压(LDO)
标签： 电源模块
上传时间： 2021-12-16
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FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
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CHAPTER 1: THE OP AMP CHAPTER 2: OTHER LINEAR CIRCUITS CHAPTER 3: SENSORS CHAPTER 4: RF/IF CIRCUITS CHAPTER 5: FUNDAMENTALS OF SAMPLED DATA SYSTEMS CHAPTER 6: CONVERTERS CHAPTER 7: DATA CONVERTER SUPPORT CIRCUITS CHAPTER 8: ANALOG FILTERS CHAPTER 9: POWER MANAGEMENT CHAPTER 10: PASSIVE COMPONENTS CHAPTER 11: OVERVOLTAGE EFFECTS ON ANALOG INTEGRATED CIRCUITS CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES CHAPTER 13: DESIGN DEVELOPMENT TOOLS
上传时间： 2021-12-21
上传用户：wangshoupeng199
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
标签： DDR4
上传时间： 2022-01-09
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这本书展示了最常见的硬开关电源拓扑和移相全桥软开关的波形和方程。所有的方程都是理想的，唯一的例外是考虑了整流二极管和续流二极管的正向电压。所有这些方程也可以在德州仪器的Power Stage Designer工具中使用。
标签： 电源
上传时间： 2022-01-13
上传用户：qdxqdxqdxqdx
高通(Qualcomm)蓝牙芯片QCC5151_硬件设计详细指导书（官方内部培训手册）共52页其内容是针对硬件设计、部分重要元器件选择(ESD，Filter）及走线注意事项的详细说明。2 Power management 2.1 SMPS 2.1.1 Components specification 2.1.2 Input power supply selection 2.1.3 Minimize SMPS EMI emissions 2.1.4 Internal LDOs and digital core decoupling 2.1.5 Powering external components 2.2 Charger 2.2.1 Charger connections.2.2.2 General charger operation2.2.3 Temperature measurement during charging 2.3 SYS_CTRL 3 Bluetooth radio3.1 RF PSU component choice 3.2 RF band-pass filter3.3 Layout (天线 走线的注意事项)4 Audio4.1 Audio bypass capacitors 4.2 Earphone speaker output4.3 Line/Mic input 4.4 Headphone output optimizition5 LED pads 5.1 LED driver 5.2 Digital/Button input 5.3 Analog input5.4 Disabled 6 Reset pin (Reset#)7 QSPIinterface 8 USB interfaces 8.1 USB device port8.1.1 USB connections8.1.2 Layout notes8.1.3 USB charger detection
上传时间： 2022-01-24
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高通蓝牙芯片QCC5051详细规格书共有117页，开发人员必备手册 支持蓝牙标准 5.2 ->Quad-core processor architecture ->High-performance programmable Bluetooth stereo audio Soc ->Low power modes to extend battery life. ->Flexible flash programmable platform. ->For wired/wirelss stereo heradsets/headphones application. ->For Qualcomm TrueWirless stereo earbuds application.主要特点如下
上传时间： 2022-01-24
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