1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses COMMON 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
上传时间： 2013-11-08
上传用户：laozhanshi111
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide COMMON-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上传时间： 2013-10-13
上传用户：ytulpx
根据看门狗电路的原理，设计出简单适用、性能可靠的1TrL型看门狗电路以及价格低廉、性能可靠的微功耗CMOS型看门狗电路，同时还介绍了常用的uP监视器O型看门狗电路。关键词：看门狗电路；1TrL型；CMOS型Abstract：In accordance with the principle of WDT (Watch Dog Timer 1circuit，design a，IT．L type WTD circuit，it is a dimple an d applicable an d reliable on performanceo Design a CMOS type WTD circuit，it is low prices and mini-power consumption。Also the article describes a COMMON uP type WTD circuit。Key word：WDT circuit；TFL type；CMOS typ e
上传时间： 2013-11-05
上传用户：685
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code COMMON to all supported development tools• Wide range of ports and examples
上传时间： 2013-10-13
上传用户：13162218709
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor COMMON hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
上传时间： 2013-11-04
上传用户：as275944189
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost COMMON form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
上传时间： 2013-10-27
上传用户：zhangyigenius
Abstract: This application note explains the hardware of different types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two different types: 5V general interface and 12V RS-232 interface. Within the 5V group a COMMON printed circuit board could be used for all circuits described. The variations can be achieved by different populations of components. The same principal is used for the 12V RS-232 interface. The population determines if it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many different configurations. For a custom application, one of the described options can be adapted to meet individual needs.
标签： iButtons Reading Writing and
上传时间： 2013-10-29
上传用户：long14578
单片机系统“PC”失控的软件措施Software Measure of GettingO uto fC ontrolfo r“PC"in S ingleC hipC omputerS ystem谧 加 春 王 晓 基 雷 小 华(江 西 理 工 大 学机 电 工 程 学 院 ，赣 州 34 10 00)摘要单片机系统在实际工业现场中可能遇到各种干扰和自身的随机性故障。现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针“PC”失控就是常见的故障之一，如果发生“PC”失控，将导致CPI工作混乱，酿成严重的事故。研究了“PC”失控的原因，并指出软件抗干扰的几种方法，有效保证单片机系统的正常工作。关键词单片机“PC”失控抗干扰Abstract Inp racticalin dustrialfi elds,th ereis v ariousin terferencea fectingo perationo fsi nglec hipc omputersy stemsa ndt hec omputersy stems。fac吨random faults饰themselves. It is very COMMON that the severe environment makes the computer systems abnormal. The program counter "PC"gettingo utof co ntorlis on eo fth ec ommonfa ults.If th isoc curs,C PUw ouldb eru nningo utof or deran din torducesse riousan cient.T hec ausesof " PC"geting out of control， studied in this paper and some countermeasures of anti-interference师software are given to ensure single chip computer systemworking properly.Keywords Single。饰computer Porgramc ounter"P C" Anti-interfeernc 在设 计 和 开发单片机系统时，一般难以周全地预计单片机系统在实际工业现场中可能遇到的各种干扰和自身的随机性故障。因此，除了采取防止和抑制干扰的各项措施外，还应该借助于软件措施克服某些干扰，系统还应具备迅速自行恢复的能力。本文介绍的应对单片机系统PC失控的软件措施，设计灵活，节省硬件资源，能保证测控系统长期可靠地运行。MC S- 5 1单片机以其优良的性能价格比大量应用于工业现场测试和控制领域。但是，现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针PC失控就是常见的故障之一，一旦发生PC“走飞”，计算机系统就会出现工作混乱，酿成严重的事故。为 了 在 CP 失控时尽量减少由此带来的不利影响，并尽快使系统恢复正常，需要采取一定的软件措施和硬件措施。常见的硬件措施有“看门狗”电路。软件措施设置的前提条件是:①在干扰作用下，微机系统硬件部分不会受到任何损坏，或者损坏部分设置有监测状态可供查询;②程序区不会受到干扰侵害。单片机系统的程序和表格以及重要的参数均设置在ROM区，不会因干扰的侵人而改变;③ RAM区中的重要数据不会被破坏，或者虽然被破坏，但是可以重新建立。
上传时间： 2013-11-02
上传用户：bhqrd30
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a COMMON on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
一篇长90页的PPT和10个左右的示例源程序，对于自学能力强且有一定计算机编程基础的人来说上手还是很快的。 •Understand the components of a Virtual Instrument •Introduce labview and COMMON labview functions •Build a simple data acquisition application •Create a subroutine in labview
上传时间： 2013-11-21
上传用户：yeling1919
