LPC master verilog source(内附LPC标准协议文档)
用户接口Wishbone bus 接口, 驱动LPC master去主动访问 slave 寄存器表(地址可更改) 读取到寄存器封装到用户层 可按要求更改设计 ...
用户接口Wishbone bus 接口, 驱动LPC master去主动访问 slave 寄存器表(地址可更改) 读取到寄存器封装到用户层 可按要求更改设计 ...
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Debugging with GDB, The GNU Source-Level Debugger Ninth Exlition,for GDB version6.6...
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simulation psk, simulation source, there are descriptions and explanations related to procedures and...