LZW压缩和解压缩程序 lzw.c 主要的功能模块 bitio.c/bitio.h 一些支撑函数，支持以比特(bit)为单位的文件I/O 用法： 压缩 lzw E <in-file> <out-file> 解压缩 lzw D <in-file> <out-file> 压缩时，读入<in-file>中内容，压缩后存入<out-file>中，得到压缩文件。 解压缩时，读入<in-file>中内容，将结果存入<out-file>中，得到原文件。 本代码在linux+gcc/windows+vc下经过测试，为了使读者容易理解算法本身， 算法实现中仅采用了简单的错误处理机制和优化。
上传时间： 2015-06-08
上传用户：chenbhdt
使用java编写的LSB图像信息隐藏算法演示程序，可以将任何符合大小限制的文件拆分为一个一个bit隐藏到非压缩bmp图像中。支持在隐藏前通过zip类对文件进行压缩
上传时间： 2015-06-09
上传用户：xuanchangri
Included are the files wav1.m, wav2.m, wavecoef.mat and readme. wav2 function implements the tree structured wavelet transform of the input matrix, up to the given level of decomposition. Wav2 uses another function called wav1, which takes the well known wavelet transform of the given matrix. Daubechies wavelet coefficients are used for wavelet transform operation wahich is saved in wavcoeff.mat.
标签： implements the wav Included
上传时间： 2015-06-23
上传用户：爱死爱死
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
标签： 8226 Programmable Compatible In-System
上传时间： 2015-06-27
上传用户：dianxin61
暂时只支持jpeg2000支持的 cdf97 和spline53 可以这样来测试： x=imread( E:\study\jpeg2000\images\lena.tif ) ％ see the decomposition coefficients y=wavelift(x, 1, spl53 ) using spline 5/3 wavelet figure subplot(1,2,1) imshow(x) subplot(1,2,2) imshow(mat2gray(y)) ％ see the reconstruction precision yy=wavelift(x, 5) using cdf 9/7 wavelet ix=wavelift(yy,-5) inverse sum(sum((double(x)-ix).^2))
标签： 2000 imageslena studyjpeg imread
上传时间： 2014-01-14
上传用户：懒龙1988
8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn
上传时间： 2015-07-02
上传用户：colinal
Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.
标签： Avalon_VGA
上传时间： 2015-07-07
上传用户：kikye
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model
标签： Algorithm Decoder DVB-RCS Release
上传时间： 2015-07-10
上传用户：清风冷雨
平均因子分解法，适用于正定矩阵First, let s recall the definition of the Cholesky decomposition: Given a symmetric positive definite square matrix X, the Cholesky decomposition of X is the factorization X=U U, where U is the square root matrix of X, and satisfies: (1) U U = X (2) U is upper triangular (that is, it has all zeros below the diagonal). It seems that the assumption of positive definiteness is necessary. Actually, it is "positive definite" which guarantees the existence of such kind of decomposition.
标签： 分解
上传时间： 2013-12-24
上传用户：啊飒飒大师的
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
