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BUS HOLD

  • 批处理感知器算法

    批处理感知器算法的代码matlab w1=[1,0.1,1.1;1,6.8,7.1;1,-3.5,-4.1;1,2.0,2.7;1,4.1,2.8;1,3.1,5.0;1,-0.8,-1.3;     1,0.9,1.2;1,5.0,6.4;1,3.9,4.0]; w2=[1,7.1,4.2;1,-1.4,-4.3;1,4.5,0.0;1,6.3,1.6;1,4.2,1.9;1,1.4,-3.2;1,2.4,-4.0;     1,2.5,-6.1;1,8.4,3.7;1,4.1,-2.2]; w3=[1,-3.0,-2.9;1,0.5,8.7;1,2.9,2.1;1,-0.1,5.2;1,-4.0,2.2;1,-1.3,3.7;1,-3.4,6.2;     1,-4.1,3.4;1,-5.1,1.6;1,1.9,5.1]; figure; plot(w3(:,2),w3(:,3),'ro'); hold on; plot(w2(:,2),w2(:,3),'b+'); W=[w2;-w3];%增广样本规范化 a=[0,0,0]; k=0;%记录步数 n=1; y=zeros(size(W,2),1);%记录错分的样本 while any(y<=0)     k=k+1;     y=a*transpose(W);%记录错分的样本     a=a+sum(W(find(y<=0),:));%更新a     if k >= 250         break     end end if k<250     disp(['a为:',num2str(a)])      disp(['k为:',num2str(k)]) else      disp(['在250步以内没有收敛,终止']) end %判决面:x2=-a2*x1/a3-a1/a3 xmin=min(min(w1(:,2)),min(w2(:,2))); xmax=max(max(w1(:,2)),max(w2(:,2))); x=xmin-1:xmax+1;%(xmax-xmin): y=-a(2)*x/a(3)-a(1)/a(3); plot(x,y)

    标签: 批处理 算法matlab

    上传时间: 2016-11-07

    上传用户:a1241314660

  • CAN原理與應用

    •CAN BUS: Controller area network(ISO-11898) 是起緣於80年代,由國際標準化組織(ISO)所 發佈,是一種應用於極嚴苛環境下的傳輸匯流排

    标签: CAN

    上传时间: 2016-11-24

    上传用户:test1111

  • CAN总线(SJA1000T、TJA1050)全套开发资料

    CAN总线(SJA1000T、TJA1050)全套开发资料,包含can-bus开发步骤,CAN学习笔记,CAN中文协议,PCA82C250周立功,SJA1000独立CAN控制器,SJA1000独立的CAN控制器应用指南

    标签: 1000T 1000 1050 CAN SJA TJA 总线 开发资料

    上传时间: 2018-05-10

    上传用户:回忆是个说书人

  • Dual USB High-Side Power Switch

    The SP2526A device is a dual +3.0V to +5.5V USB Supervisory Power Control Switch ideal for self-powered and bus-powered Universal Serial Bus (USB) applications. Each switch has low on-resistance (110mΩ typical) and can supply 500mA minimum. The fault currents are limited to 1.0A typical and the flag output pin for each switch is available to indicate fault conditions to the USB controller. The thermal shutdown feature will prevent damage to the device when subjected to excessive current loads. The undervoltage lockout feature will ensure that the device will remain off unless there is a valid input voltage present.

    标签: High-Side Switch Power Dual USB

    上传时间: 2019-03-06

    上传用户:bhitr

  • L9945

    AEC-Q100 qualified • 12 V and 24 V battery systems compliance • 3.3 V and 5 V logic compatible I/O • 8-channel configurable MOSFET pre-driver – High-side (N-channel and P-channel MOS) – Low-side (N-channel MOS) – H-bridge (up to 2 H-bridge) – Peak & Hold (2 loads) • Operating battery supply voltage 3.8 V to 36 V • Operating VDD supply voltage 4.5 V to 5.5 V • All device pins, except the ground pins, withstand at least 40 V • Programmable gate charge/discharge currents for improving EMI behavior

    标签: configurable Automotive pre-driver suitable channel systems MOSFET fully High side

    上传时间: 2019-03-27

    上传用户:guaixiaolong

  • can bus fpga实现源码

    用verilog写的can总线代码,包括ram读写等操作,需要对can总线有一定的了解。

    标签: fpga can bus 源码

    上传时间: 2019-10-10

    上传用户:fwloveu

  • PCI2.2规范

    PCI2.2规范,PCI Local Bus Specification Revision 2.2 December 18, 1998

    标签: PCI2.2规范

    上传时间: 2019-11-05

    上传用户:songpenghai

  • Capture 自带元件库List

    AMPLIFIER.OLB ARITHMETIC.OLB ATOD.OLB BUS DRIVERTRANSCEIVER.OLB CAPSYM.OLB CONNECTOR.OLB COUNTER.OLB DISCRETE.OLB 等

    标签: Capture List 元件库

    上传时间: 2020-03-03

    上传用户:llik

  • LPC master verilog source(内附LPC标准协议文档)

    用户接口Wishbone bus 接口, 驱动LPC master去主动访问 slave 寄存器表(地址可更改) 读取到寄存器封装到用户层 可按要求更改设计

    标签: LPC Wishbone Verilog Specification

    上传时间: 2020-05-21

    上传用户:verilog_86

  • Cooperative+Communications

    Cooperation is not a natural characteristic attributed to humans. The typical human horizon is focused on short-term gains, which might be due to our instinct-driven subconscious occupying a grander importance than we dare to admit [1]. Cooperating with other individuals or entities, however, usually means that short-term losses may translate into long-term gains – something history has proved to hold true but humans for some reason rarely ever understand. 

    标签: Communications Cooperative

    上传时间: 2020-05-27

    上传用户:shancjb