FPGA-Seven segment and counter
FPGA-Seven segment and counter...
FPGA-Seven segment and counter...
数码管现实bcd码的解码过程,0000-1001用数码管现实译码结果...
VHDL Design of BCD to 7-segment decoder using PROM...
This is a counter led example developed in ISE....
avr atmega168v Timer counter的程序,可以使用...
EDA 十进制计数器、BCD VHDL源代码...
BCD=Boot Configuration Data (启动设置数据) ,BCD是操作系统中的启动设置数据, 在有vista或windows7的多重操作系统中,系统通bootmgr程序导入BC...
实现一位BCD码的加法,并且带有进位。还可以利用逻辑电路实现此功能。...
Up down counter for microchip ASM code tested...
a counter t in vhdl with flip-flop tipe t...