源码文件
V 51 K 126370352000 88e1111-rcj |R 0:19_3-21-06 Y 1 D 0 0 290 900 Z 10 i 155 U 0 -40 10 0 3 0 LEVEL=STD U 0 -30 10 0 3 0 P…
Analog+Design 源代码
汇集 Analog+Design 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
V 51 K 49316356990 hfj11_1g01e |R 21:49_4-6-06 Y 1 D 0 0 240 240 Z 10 i 42 U 0 -10 10 0 3 3 DEVICE=RJ45_HFJ11-1G01E U 0 -2…
源码文件
anacrypt -i ANALOG.SRC -o license.dat exit
源码文件
anacrypt -i ANALOG.SRC -o license.dat exit
源码文件
DE2_Default ----------- This design is the initial design when the board is powered-up. It increments a counter and displays t…
源码文件
Release 7.1.04i Map H.42 Xilinx Mapping Report File for Design 'serial' Design Information ------------------ Command Line : D:…
源码文件
Release 7.1.04i Map H.42 Xilinx Mapping Report File for Design 'clk' Design Information ------------------ Command Line : D:/Xi…
源码文件
DE2_i2sound ----------- This design combines audio input from the microphone and line in signals and outputs the result to the…
源码文件
Design: 9:54 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\countersure\countersure.adf" Design: Error: C:\My…
源码文件
Design: 1:45 PM, Sunday, April 12, 2009 Design: Opening design "C:\My Designs\tff\tff.adf" ELBREAD: Elaboration process. ELBREA…