console.log

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

Design: 9:54 PM, Tuesday, March 31, 2009
Design: Opening design "c:\my designs\countersure\countersure.adf"
Design: Error: C:\My Designs\countersure\src\VHDL code1.vhd cannot be compiled.
Compilation...
File: .\src\VHDL code1.vhd
Compile Entity "count2"
Compile Architecture "behaviour" of Entity "count2"
Compile success 0 Errors 0 Warnings  Analysis time :  0.0 [s]
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
KERNEL: Main thread initiated.
KERNEL: Kernel process initialization phase.
ELAB2: Elaboration final pass...
ELAB2: Elaboration final pass complete - time: 0.0 [s].
KERNEL: Kernel process initialization done.
9:54 PM, Tuesday, March 31, 2009
Simulation has been initialized
Selected Top-Level: count2 (behaviour)
Signal T not found in design
Signal CLK not found in design
Signal Q not found in design
Signal QINV not found in design
Cannot force signal T with formula 0 0, 1 100000 -r 200000.
Cannot force signal CLK with formula 0 0, 1 50000 -r 100000.
Simulation has been stopped