timestamp=1145801594109 [cordic_add] A/rtl=21|g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_add_rtl…
Altera+SoC 源代码
汇集 Altera+SoC 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
iG:\2006春季课程\通信系统仿真与SOC集成-周祖成-2005春\1_A_作业\HDesign\HDesign_lib\hdl\cordic_add_rtl.vhd iG:\2006春季课程\通信系统仿真与SOC集成-周祖成-2005春\1_A_作业\…
[Project] Current Flow=Multivendor VCS=0 version=1 Current Config=compile [Configurations] compile=cordic_beh [Library]…
58 ~E 1 "g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_testbench_struct.vhd" 13 cordic_testbench ~E 1 "…
"g:\2006春季课程\通信系统仿真与SOC集成-周祖成-2005春\1_A_作业\HDesign\HDesign_lib\hdl\cordic_add_rtl.vhd" cordic_beh 1 0 1819696179 "g:\2006春季课程\通信系…
-w -s "E:\Program Files\active_hdl_designs\cordic_beh\library.cfg" -j "E:\Program Files\active_hdl_designs\cordic_beh\projlib.cfg…
/******************************************************************** * Filename: 74HC165_button.c *********************…
F:/课程/SOC设计/作业/shifttest/zhengshi/db/shift.sim.vwf 0 106832 616 106832 0 F:/课程/SOC设计/作业/shifttest/zhengshi/shift.vwf 0 75500 755 …