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Java编程 A simple blackjack game. New graphics, added sounds. Features: dealing, hitting, standing, insurance
A simple blackjack game. New graphics, added sounds. Features: dealing, hitting, standing, insurance, and money.
VHDL/FPGA/Verilog 3. Distribution of this core must be free of charge. Charging is -- allowed only for value added ser
3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products.
Java编程 - MP3 streaming support for Shoutcast/Icecast added. - Ogg Vorbis support added. - Playlist implem
- MP3 streaming support for Shoutcast/Icecast added.
- Ogg Vorbis support added.
- Playlist implementation and M3U support added.
- JavaLayer 0.1.1 included to improve MP3 support.
- WinAmp Skins 2.0 support improved.
- Seek bar added (for WAV files only).
数值算法/人工智能 用c/c++产生源码. 本人平时收集的. 主要用于算法仿真. Park and Miller with Bays-Durham shuffle and added safeguards
用c/c++产生源码. 本人平时收集的.
主要用于算法仿真.
Park and Miller with Bays-Durham shuffle and added safeguards
其他 avs decoder sources, added a command line sample
avs decoder sources, added a command line sample
SCSI/ASPI With OpenSSL 0.9.6, a new component has been added to support external crypto devices, for example a
With OpenSSL 0.9.6, a new component has been added to support external crypto devices, for example accelerator cards. The component is called ENGINE, and has still a pretty experimental status and almost no documentation. It s designed to be fairly easily extensible by the calling programs.
软件设计/软件工程 REVISIONS: 11/22/02 - DM: Added support for switches and sample USB
REVISIONS: 11/22/02 - DM: Added support for switches and sample USB
其他 更新内容： 1 增加了搜索功能 2 提供了帮助页面 修改若干小问题 管理名称 admin 初始密码：admin-update : added a search function to help pro
更新内容： 1 增加了搜索功能 2 提供了帮助页面 修改若干小问题 管理名称 admin 初始密码：admin-update : added a search function to help provide two pages of small amendments to a number of issues management initial name admin Password : admin
系统设计方案 Fast settling-time added to the already conflicting requirements of narrow channel spacing and low
Fast settling-time added to the already conflicting requirements of narrow channel spacing and
low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator ...
VHDL/FPGA/Verilog This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added commen
This Verilog HDL description implements a UART
Version 1.1 : Original Creation
2.1 : added comments