Active-HDL
Active-HDL是一款功能强大的硬件描述语言仿真工具，专为FPGA/CPLD设计验证而生。它支持VHDL、Verilog和SystemC等多种语言，提供直观的图形界面与高效的调试环境，极大提升了数字电路开发效率。无论是初学者还是资深工程师，都能通过丰富的示例项目快速掌握复杂系统的设计技巧。加入我...
资源总数
809
Active-HDL 全部资料 809 份
three_phase_four_wires_id_iq active filter in matlab&simulink
three_phase_four_wires_id_iq active filter in matlab&simulink
2017-07-23
111
Active component schematic library for altium
Active component schematic library for altium
2014-01-12
102
Active Filter Evaluation Board for Differential Amplifiers
The boards also have provisions for edge-mounted SMA connectors, which simplify testing and integ
2023-12-02
1
Study of Active Queue Management Using OPNET
Study of Active Queue Management Using OPNET
2015-12-16
105