Active-HDL
Active-HDL是一款功能强大的硬件描述语言仿真工具，专为FPGA/CPLD设计验证而生。它支持VHDL、Verilog和SystemC等多种语言，提供直观的图形界面与高效的调试环境，极大提升了数字电路开发效率。无论是初学者还是资深工程师，都能通过丰富的示例项目快速掌握复杂系统的设计技巧。加入我...
资源总数
500
Active-HDL 全部资料 500 份
Verilog HDL Synthesis, A Practical Primer 学习Verilog HDL一本很不错的英文书
Verilog HDL Synthesis, A Practical Primer 学习Verilog HDL一本很不错的英文书，比较透彻
2016-01-19
147
GTRACK Track mouse position and show coordinates in figure title. Once GTRACK is active the mouse
GTRACK Track mouse position and show coordinates in figure title. Once GTRACK is active the mouse position is constan...
2013-12-17
103
Hi This mfile is source code for image segementation using active contour models [Snake]. It found
Hi This mfile is source code for image segementation using active contour models [Snake]. It found the objects in imaag...
2013-12-31
177