A Top-Down Verilog-A Design on the digital phase-lockedmloop
A Top-Down Verilog-A Design on the digital phase-lockedmloop
A-P技术汇集了从模拟到数字、电源管理到信号处理的全方位解决方案,是电子工程师不可或缺的知识宝库。本页面收录了12774个精选资源,涵盖电路设计、嵌入式系统开发及自动化控制等多个领域,旨在帮助您快速掌握最新技术趋势与实践技巧。无论是初学者还是资深开发者,都能在这里找到适合自己的学习材料和技术文档,助...
A Top-Down Verilog-A Design on the digital phase-lockedmloop
A project by word about a fee collection system on highway
its a ofdma simulink model. with a modulation scheme on 8psk
a bout union_find set , which is a very useful data structrue.
a genetic algorithm to find the maximum of a polynomial function
this is a sample of a java bot. use to educate..
A code that show the count back to a date determinate.
Program that demonstrates a socket connection in a mobile phone scenario.
Displaying A Picture On A 128x64 Graphical LCD Using PIC 16f877
Description of a sistolic arhictecture for a FFT implementation in FPGA.