代码搜索：xilinx ise 开发教程

找到约 10,000 项符合「xilinx ise 开发教程」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/174928/9568084

log __projnav.log

Project Navigator Auto-Make Log File ------------------------------------- deleting __projnav/buzhidao.gfl Finished cleaning up project Project Navigator Auto-Make Log File --------------------
·
www.eeworm.com/read/174928/9568106

syr sdrm.syr

Release 6.3i - xst G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 2.50 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set to
·
www.eeworm.com/read/358544/10185630

sav my.convert.sav

`timescale 1ns/1ns `include "my.v" `include "E:/Xilinx/verilog/src/iSE/unisim_comp.v"
·
www.eeworm.com/read/358544/10185662

sprj my.sprj

`timescale 1ns/1ns `include "my.v" `include "E:/Xilinx/verilog/src/iSE/unisim_comp.v"
·
www.eeworm.com/read/308751/13693385

prm tst1.prm

PROMGEN: Xilinx Prom Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o E:\ise6.1\tst//tst1 -u 0 E:\ise6.1\tst\tst.bit -x xcf04s PROM E:\ise6.1\
·
www.eeworm.com/read/308751/13693755

prm dingarm.prm

PROMGEN: Xilinx Prom Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o E:\ise6.1\tst//dingarm -u 0 E:\ise6.1\tst\top.bit -x xcf04s PROM E:\ise6
·
www.eeworm.com/read/308751/13693826

prm ding2.prm

PROMGEN: Xilinx Prom Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o E:\ise6.1\tst//DING2 -u 0 E:\ise6.1\tst\top.bit -x xcf04s PROM E:\ise6.1
·
www.eeworm.com/read/308751/13693876

prm armtst.prm

PROMGEN: Xilinx Prom Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o E:\ise6.1\tst//armtst -u 0 E:\ise6.1\tst\armtst.bit -x xcf04s PROM E:\is
·
www.eeworm.com/read/219736/14866574

prj se_pa_tst_bencher.prj

verilog work "se_pa.v" verilog work D:/Software/Xilinx ISE8.2/verilog/src/glbl.v
·
www.eeworm.com/read/154076/5642959

sprj and5or2.sprj

`timescale 1ns/1ns `include "and5or2.vf" `include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
·