sdrm.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 2.50 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.52 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: sdrm.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sdrm.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sdrm
Output Format                      : NGC
Target Device                      : xc3s50-4-pq208

---- Source Options
Top Module Name                    : sdrm
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : ONLY
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sdrm.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sdrmc_state.vhd in Library work.
Architecture sdrmc_state_arch of Entity sdrmc_state is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/cslt_cntr.vhd in Library work.
Architecture cslt_cntr_arch of Entity cslt_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/brst_cntr.vhd in Library work.
Architecture brst_cntr_arch of Entity brst_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/rcd_cntr.vhd in Library work.
Architecture rcd_cntr_arch of Entity rcd_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd in Library work.
Architecture ref_cntr_arch of Entity ref_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/ki_cntr.vhd in Library work.
Architecture ki_cntr_arch of Entity ki_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd in Library work.
Architecture sdrm_t_arch of Entity sdrm_t is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sys_int.vhd in Library work.
Architecture sys_int_arch of Entity sys_int is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sdrm.vhd in Library work.
Entity <sdrm> (Architecture <sdrm_arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sdrm> (Architecture <sdrm_arch>).
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 238: Generating a Black Box for component <IBUFG>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 242: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 245: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 245: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 245: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 245: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 250: Generating a Black Box for component <OBUF_F_16>.
WARNING:Xst:753 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 254: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 254: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 254: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 254: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 260: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 261: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 316: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 317: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 318: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 319: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 320: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 321: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 322: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 323: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 324: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 325: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 326: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 327: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 328: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 329: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 330: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 331: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 332: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 333: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 334: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 335: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 336: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 337: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 338: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 339: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 340: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 341: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 342: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 343: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 344: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 345: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 346: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 347: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 350: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 351: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 352: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 353: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 354: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 355: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 356: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 357: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 358: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 359: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 360: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 361: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 362: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 363: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 364: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 365: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 366: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 367: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 368: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 369: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 370: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 371: Generating a Black Box for component <OBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 374: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 375: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 376: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 378: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 379: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 380: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 381: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 382: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 383: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 384: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 385: Generating a Black Box for component <IOBUF_F_12>.