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半加器 [3-15]------------(1)半加器描述:布尔方程描述法 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a,b: IN STD_LOGIC; co,so: OUT STD_LOGIC); END ENTITY h_adder; ARCHITECTURE f

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www.eeworm.com/read/176099/9516662

vhdl bench.vhdl

-- $Id: bench.vhdl,v 1.1.1.1 2005/01/04 02:05:56 arif_endro Exp $ ------------------------------------------------------------------------------- -- Title : Test Bench -- Project : FM Receiv

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www.eeworm.com/read/176099/9516673

vhdl fulladder.vhdl

-- $Id: fulladder.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $ ------------------------------------------------------------------------------- -- Title : Full Adder component -- Project

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www.eeworm.com/read/176099/9516685

vhdl fm.vhdl

-- $Id: fm.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $ ------------------------------------------------------------------------------- -- Title : FM core component -- Project : FM Re

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