代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
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www.eeworm.com/read/32453/1034238
100vhdl+
--Page : 282
--Objective : Infinite oscillation in delta time domain
--Filename :test_13
--Author :Joseph Pick
entity Test_13 is
end Test_13;
architecture Behave_1 of Test_1
www.eeworm.com/read/32453/1034239
100vhdl+
www.eeworm.com/read/32453/1034240
100vhdl+
function bit_to_int (in1:bit_vector) return integer is
ALIAS v1: BIT_VECTOR(in1'LENGTH-1 DOWNTO 0) IS in1;
variable inpv : bit_vector(in1'LENGTH-1 DOWNTO 0 );
variable SUM: integer
www.eeworm.com/read/32453/1034241
100vhdl+
www.eeworm.com/read/32453/1034242
100vhdl+
--以下是部件声明的包
--部件mem_sequence,mem_string，以及协处理器分别在以下的包pkg_components中进行了说明
--每一个内存块中包括一个局部控制器，该局部控制器管理一个双向端口的RAM
--其中26-36行是mem_sequence的
--73-83行是mem_string的
--实际上每一个双端RAM都将其自己封装为真正的RAM部件
LIBR
www.eeworm.com/read/32453/1034243
100vhdl+
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE work.pkg_types.ALL;
ENTITY top IS
PORT ( clk : IN bit1;
reset : IN bit1;
www.eeworm.com/read/32453/1034244
100vhdl+
--这是子类型和部件声明的包
--用于区分向量类型的不同宽度
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
PACKAGE pkg_types IS
SUBTYPE bit1 IS std_ulogic;
SUBTYPE bit
www.eeworm.com/read/32453/1034245
100vhdl+
--wss为一个组装程序，把mem_string,mem_sequence,co_processor
--和top controller组装为一个系统
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
--USE ieee.std_logic_unsigned.ALL;
www.eeworm.com/read/32453/1034246
100vhdl+
--Page :303 304
--Objective :Efficient command decoding
--Filename :test_67b.vhd
--Author :Joseph Pick
entity Test_67b is
end Test_67b;
architecture Behave_1
www.eeworm.com/read/32453/1034247
100vhdl+
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of