100vhdl+

100vhdl例子

LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;
   USE ieee.std_logic_arith.ALL;
   USE work.pkg_types.ALL;
  
ENTITY top IS 
PORT ( clk         : IN   bit1;
       reset       : IN   bit1;
       command     : IN   bit1;
       c_sel       : OUT  bit1;
       s_sel       : OUT  bit1;
       burst       : OUT  bit2_r;
       p_sel       : OUT  bit1;
       mode        : OUT  bit1;
       c_done      : IN   bit1;
       s_done      : IN   bit1;
       done0       : IN   bit1;
       done1       : IN   bit1;
       status      : OUT  bit1);
END top;

ARCHITECTURE behavior OF top IS
CONSTANT n          :integer:=2;
SIGNAL  burst_int   :bit2_r;
BEGIN
 PROCESS
 BEGIN
  --初始化
  mode <= '0';
  burst_int <= "00";
  p_sel <= '0';
  c_sel <= '0';
  s_sel <= '0';
  status <='0';
  main_loop : LOOP    
    --等到所有组件都准备就绪  
    WAIT UNTIL c_done='1' AND reset='1' AND rising_edge(clk) AND
               s_done='1' AND done0='1' AND done1='1';
    status <= '1';
    --等命令的到来
    IF command /='1' THEN 
      
       WAIT UNTIL command='1' AND reset='1' AND rising_edge(clk);
    END IF;
    --设定初始工作信号，但co_processor不为最后一个处理过程
    mode <='0';
    burst_int <="00";
    status <='0';
    c_sel <='1';
    s_sel <='1';
    --等到mem_string和mem_sequence有应答信号
    WAIT UNTIL c_done='0' AND s_done='0' AND rising_edge(clk);
    
    --选定信号复位
    c_sel <='0';
    s_sel <='0';

    --等到mem_string和mem_sequence的装载过程处理完成
    WAIT UNTIL c_done='1' AND s_done='1' AND rising_edge(clk);   
    
    IF reset/='1' THEN 
       EXIT main_loop;
    END IF;
    --mem_string装载下一个burst
    burst_int <= burst_int + 1;
    s_sel <='1';
 
    WAIT UNTIL s_done='0' AND rising_edge(clk);   

    s_sel <='0';
 
    WAIT UNTIL s_done='1' AND rising_edge(clk);

    IF reset/='1' THEN 
        EXIT main_loop;
    END IF;
    --当burst_int在范围内，找出与mem_sequence中最相近的burst    
    WHILE burst_int < n AND reset='1' LOOP
       burst_int <= burst_int + 1;
       s_sel <='1';
       p_sel <='1';
      
       WAIT UNTIL s_done='0' AND done0='0' AND rising_edge(clk);

       s_sel <='0';
       p_sel <='0';

       WAIT UNTIL s_done='1' AND done0='0' AND rising_edge(clk);
    END LOOP;
    IF reset/='1' THEN 
       EXIT main_loop;
    END IF;
    --说明co_processor为最后一个处理过程
    mode <='1';
    p_sel <='1';

    WAIT UNTIL done1='1' AND rising_edge(clk);
   END LOOP main_loop;
 END PROCESS;

 burst <=burst_int;
END behavior;