代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/151500/12204107
lex vhdl.lex
%{
/************** VHDL scanner in LEX format **********
*
* Version 0.2 Wed Aug 11, 1993
*
* This scanner is derived from a scanner of the ALLIANCE CAD toolset,
* release 1.1. That toolset
www.eeworm.com/read/151500/12204111
y vhdl.y
/************** Syntax for VHDL in YACC format ******************
*
* Version 0.2 Wed Aug 11, 1993
*
* The original was a VHDL parser description to be used with GMD Compiler
* Tool Box
*
www.eeworm.com/read/151500/12204116
v vhdl.v
#############################################################################
# U N R E G I S T E R E D C O P Y
#
# You are on day 6 of your 30 day trial period.
#
# This
www.eeworm.com/read/338416/12307770
pdf vhdl.pdf
www.eeworm.com/read/250741/12387037
doc vhdl.doc
www.eeworm.com/read/232359/14196618
vhdl fifo.vhdl
-------------------------------------------------------------------------------
--
-- Copyright Jamil Khatib 1999
--
--
-- This VHDL design file is an open design; you can redistribute it and/or
--
www.eeworm.com/read/229548/14330393
pdf vhdl实用.pdf
www.eeworm.com/read/229106/14353266
vhdl jx.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Phase_Meter is
Port ( ina : in std_logic;
inb : in std_logic;
clk : in std_logi
www.eeworm.com/read/227241/14436283
jsf vhdl.jsf
# JOE syntax highlight file for VHDL
# Define colors
=Idle
=Comment green
=Constant cyan
=Escape bold cyan
=Keyword bold
=Operator bold
# All following states are for when we're not in a preprocess
www.eeworm.com/read/227241/14436296
in vhdl.jsf.in
# JOE syntax highlight file for VHDL
# Define colors
=Idle
=Comment green
=Constant cyan
=Escape bold cyan
=Keyword bold
=Operator bold
# All following states are for when we're not in a preprocess