jx.vhdl

相位比较器的VHDL实现程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Phase_Meter is

    Port ( ina : in std_logic;
           inb : in std_logic;
           clk : in std_logic;
           disp3 : out std_logic_vector(6 downto 0);
           disp2 : out std_logic_vector(6 downto 0);
           disp1 : out std_logic_vector(6 downto 0);
           disp0 : out std_logic_vector(6 downto 0));

end Phase_Meter;


architecture Behavioral of Phase_Meter is

    signal ina1,inb1,ina2,inb2,inafall,inbfall,PD : std_logic := '0';
    signal NUM1,NUM2 : integer range 0 to 16384 := 0;
    signal NUMCNT : integer range 0 to 4080:= 0;
    signal ENNUM,LOAD,RESET : std_logic := '0';
    signal dp3,dp2,dp1,dp0 : std_logic_vector(3 downto 0) := "0000";

begin

    
    process(clk)
    begin
        if clk'event and clk = '1' then
            ina1 <= ina; ina2 <= ina1; inafall <= ina1 and (not ina2);
		  inb1 <= inb; inb2 <= inb1; inbfall <= inb1 and (not inb2);
		  if inafall = '1' then
		     PD <= '1'; 
		  end if;
		  if inbfall = '1' then 
		     PD <= '0'; 
		  end if;
        end if;
    end process;
    process(clk)
    begin
        if clk'event and clk = '1' then
	      NUM1 <= NUM1 + 1;							    
		  if NUM1 = 16383 then							
		      NUMCNT <= NUMCNT + 1;										 
			 if NUMCNT = 0 then 
			    ENNUM <= '1';			                       
                elsif NUMCNT = 3600 then 
			       ENNUM <= '0'; 
		      end if;			               
			 if NUMCNT = 3840 then 
			    LOAD <= '1'; 
			 else LOAD <= '0'; 
			 end if;	
			 if NUMCNT = 4080 then 
			    RESET <= '1'; 
			 else RESET <= '0'; 
			 end if;	 
            end if;
		  if RESET = '1' then
		      NUM2 <= 0;
			 dp0 <= "0000";
			 dp1 <= "0000";
			 dp2 <= "0000";
			 dp3 <= "0000";
		  elsif ENNUM = '1' and PD = '1' then
		      NUM2 <= NUM2 + 1;	                                     
			 if NUM2 = 16383 then
			     if dp0 = "1001" then									
				    dp0 <= "0000";									
				    if dp1 = "1001" then								
				        dp1 <= "0000";								
					   if dp2 = "1001" then							
				            dp2 <= "0000";							
						  if dp3 = "1001" then						
				                dp3 <= "0000";							
                                else									
						      dp3 <= dp3 + 1;							
                                end if;										
                            else										
						  dp2 <= dp2 + 1;								
                            end if;										
                        else												 
                            dp1 <= dp1 + 1;									
                        end if;										
                    else												
			         dp0 <= dp0 + 1;									
                    end if;											
                end if;												
            end if;													
	end if;
    end process;
 process(clk)
 begin
 if  LOAD='1' then
 case dp0 is
		          when "0000" => disp0 <= "0000001";
		          when "0001" => disp0 <= "1001111";
			     when "0010" => disp0 <= "0010010";
		          when "0011" => disp0 <= "0000110";
		          when "0100" => disp0 <= "1001100";
		          when "0101" => disp0 <= "0100100";
		          when "0110" => disp0 <= "0100000";
		          when "0111" => disp0 <= "0001111";
		          when "1000" => disp0 <= "0000000";
		          when "1001" => disp0 <= "0000100";
		          when others => disp0 <= "-------";
 end case;
 case dp1 is
		          when "0000" => disp1 <= "0000001";
		          when "0001" => disp1 <= "1001111";
		 	     when "0010" => disp1 <= "0010010";
			     when "0011" => disp1 <= "0000110";
			     when "0100" => disp1 <= "1001100";
			     when "0101" => disp1 <= "0100100";
			     when "0110" => disp1 <= "0100000";
			     when "0111" => disp1 <= "0001111";
			     when "1000" => disp1 <= "0000000";
			     when "1001" => disp1 <= "0000100";
			     when others => disp1 <= "-------";
 end case;
 case dp2 is
		          when "0000" => disp2 <= "0000001";
			     when "0001" => disp2 <= "1001111";
			     when "0010" => disp2 <= "0010010";
			     when "0011" => disp2 <= "0000110";
			     when "0100" => disp2 <= "1001100";
			     when "0101" => disp2 <= "0100100";
			     when "0110" => disp2 <= "0100000";
			     when "0111" => disp2 <= "0001111";
			     when "1000" => disp2 <= "0000000";
			     when "1001" => disp2 <= "0000100";
			     when others => disp2 <= "-------";
 end case;
 case dp3 is
			     when "0000" => disp3 <= "0000001";
			     when "0001" => disp3 <= "1001111";
			     when "0010" => disp3 <= "0010010";
			     when "0011" => disp3 <= "0000110";
			     when "0100" => disp3 <= "1001100";
			     when "0101" => disp3 <= "0100100";
		          when "0110" => disp3 <= "0100000";
			     when "0111" => disp3 <= "0001111";
			     when "1000" => disp3 <= "0000000";
			     when "1001" => disp3 <= "0000100";
			     when others => disp3 <= "-------";
 end case;
 end if;
 end  process;    

end Behavioral;