代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/477743/6733676
vhdl blowfishsbox.vhdl
-- Copyright © 2007 Wesley J. Landaker
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis
www.eeworm.com/read/477743/6733677
vhdl blowfishcipher.vhdl
-- Copyright © 2007 Wesley J. Landaker
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis
www.eeworm.com/read/477743/6733679
vhdl blowfishround.vhdl
-- Copyright © 2007 Wesley J. Landaker
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis
www.eeworm.com/read/477377/6742341
vhdl testbenchri.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity instr_reg_test is
end entity;
architecture arch of instr_reg_test is
signal done : boolean := fa
www.eeworm.com/read/477377/6742369
vhdl flag.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity status_reg is
port ( clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
i : in std_logic_vector(3 downto 0)
www.eeworm.com/read/477377/6742370
vhdl bancregistre.vhdl
LIBRARY ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg_file is
port( clk: in std_logic;
www.eeworm.com/read/477377/6742373
vhdl ri.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity instr_reg is
port(
CLK : in std_logic;
ce : in std_logic;
rst : in std_logic;
instr :in std_logic_vector(15 downto 0);
cond : out std_logi
www.eeworm.com/read/477377/6742374
vhdl testbenchregflag.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity status_reg_test is
end entity;
architecture arch of status_reg_test is
signal done : boolean := false;
signal p
www.eeworm.com/read/477377/6742377
vhdl testbenchbancregister.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity reg_file_test is
end entity;
architecture arch of reg_file_test is
signal done : boolean := false;
signal passed
www.eeworm.com/read/476862/6752284