flag.vhdl

source and benchmark test for the registery parts of a RISC processor

library ieee;
use ieee.std_logic_1164.all;
entity status_reg is
  port ( clk : in  std_logic;
         ce  : in  std_logic;
         rst : in  std_logic;

         i : in  std_logic_vector(3 downto 0);
         o : out std_logic_vector(3 downto 0) );
end entity;

architecture arch of status_reg is
begin
process 
variable Zin_reg, Nin_reg, Cin_reg, Vin_reg: std_logic;
begin
if clk = '1' and clk'event then
      if rst ='1'then 
        
         Zin_reg := 'Z';
         Nin_reg := 'Z';
         Cin_reg := 'Z';
         Vin_reg := 'Z';
      else  -- else de reset
        if ce='1'then
         Zin_reg := i(3);
         Nin_reg := i(2);
         Cin_reg := i(1);
         Vin_reg := i(0);
      end if;--end de enable
    end if;--end de reset
end if;--end de clk
-- modification des signaux de sortie
o(3) <= Zin_reg ;
o(2) <= Nin_reg ;
o(1) <= Cin_reg ;
o(0) <= Vin_reg ;
-- attente du prochain 関閚ement sur l?un des signaux d?entr閑
wait on clk;
end process;
end architecture arch;