代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585626
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
www.eeworm.com/read/159314/5585641
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuftn_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5585644
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5585645
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnsn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5585647
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_03 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585648
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_17 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585672
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_02 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585674
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_43 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585684
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufd_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585708
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2_s36 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer