_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity iobufnsn_f_24 is
    port(
        o               : out    vl_logic;
        io              : inout  vl_logic;
        i               : in     vl_logic
    );
end iobufnsn_f_24;