代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585216
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585223
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_aurora_4 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_fl
www.eeworm.com/read/159314/5585227
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut1 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
www.eeworm.com/read/159314/5585230
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s2_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
www.eeworm.com/read/159314/5585242
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity md0 is
generic(
cds_action : string := "ignore"
);
port(
i : out vl_logic
);
end md0;
www.eeworm.com/read/159314/5585249
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity osc4 is
generic(
cds_action : string := "ignore";
period : integer := 100
);
port(
f8m
www.eeworm.com/read/159314/5585254
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fd_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585255
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585264
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufns_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585265
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rdclk is
generic(
cds_action : string := "ignore"
);
port(
i : in vl_logic
);
end rdclk;