_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity lut1 is
    generic(
        init            : integer := 0
    );
    port(
        o               : out    vl_logic;
        i0              : in     vl_logic
    );
end lut1;