代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584973
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufdn_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584980
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584986
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584987
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_27 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584989
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5584991
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_31 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584992
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
www.eeworm.com/read/159314/5584997
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity vcc is
generic(
cds_action : string := "ignore"
);
port(
p : out vl_logic
);
end vcc;
www.eeworm.com/read/159314/5585001
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_35 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5585002
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=