代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584795
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity md2 is
generic(
cds_action : string := "ignore"
);
port(
i : out vl_logic
);
end md2;
www.eeworm.com/read/159314/5584797
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_gtl_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5584802
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_07 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
www.eeworm.com/read/159314/5584809
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s18 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
www.eeworm.com/read/159314/5584813
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufe is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
www.eeworm.com/read/159314/5584815
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584819
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
www.eeworm.com/read/159314/5584822
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
www.eeworm.com/read/159314/5584823
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufen is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
www.eeworm.com/read/159314/5584831
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l