代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/408281/11400060
qmsg ps2.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/406252/11445769
qsf plvji.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/405985/11451886
hif twice.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
www.eeworm.com/read/405978/11452059
hif freq2_2.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
www.eeworm.com/read/402450/11534598
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/402450/11534645
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/348172/11608448
qsf frequency_divider.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/347114/11690385
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20ke_upcore is
generic(
processor : string := "ARM";
source : string := "";
sdram_width : integer
www.eeworm.com/read/347114/11690444
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/347114/11690604
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode