代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/331193/12839742
qsf ps2tolcd.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/329297/12962827
qmsg idct.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/329297/12962896
qmsg prev_cmp_idct.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/326615/13129564
hif secondwatch.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
35
1941
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
www.eeworm.com/read/325465/13204938
qsf ps2tolcd.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/137348/13327289
make_fpga
verilog ../../../syn/src/verilog/oc8051_fpga_top.v ../../../bench/verilog/oc8051_fpga_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_
www.eeworm.com/read/321790/13398573
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dpram8x32 is
port(
data : in vl_logic_vector(7 downto 0);
wren : in vl_logic;
wraddress
www.eeworm.com/read/321790/13398700
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode
www.eeworm.com/read/321790/13398845
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
mo : out vl_logic_vector(15 downto 0);
a : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/321790/13398863
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mf_pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logi