代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/457629/7322134
hif vga_dis.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
36
1980
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
www.eeworm.com/read/455890/7362156
qsf fcout.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/454468/7389476
hif basegate.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
www.eeworm.com/read/454458/7389997
hif keyled.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
www.eeworm.com/read/453101/7426841
qmsg myled.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/452945/7428869
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity regfile is
port(
clk : in vl_logic;
we3 : in vl_logic;
ra1 : in vl_logic_v
www.eeworm.com/read/452945/7428872
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity top_tb is
generic(
CLK_CYCLE : integer := 50
);
end top_tb;
www.eeworm.com/read/452945/7428875
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity flopr is
port(
clk : in vl_logic;
reset : in vl_logic;
pcwrite : in vl_logic;
www.eeworm.com/read/452945/7428878
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
port(
clk : in vl_logic;
reset : in vl_logic;
pc : out vl_logic_vecto
www.eeworm.com/read/452945/7428894
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux2 is
generic(
WIDTH : integer := 8
);
port(
data0 : in vl_logic_vector;
data1