代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/468753/6987209
voptdg279n
library verilog;
use verilog.vl_types.all;
entity arm7 is
port(
nOPC : out vl_logic;
nCPI : out vl_logic;
CPA : in vl_logic;
www.eeworm.com/read/468753/6987227
vopt2ma6iv
library verilog;
use verilog.vl_types.all;
entity add4 is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
www.eeworm.com/read/468753/6987254
voptgqt9w3
library verilog;
use verilog.vl_types.all;
entity sub4 is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
www.eeworm.com/read/468753/6987279
vopta8yk90
library verilog;
use verilog.vl_types.all;
entity mux4 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987288
vopti0bn3i
library verilog;
use verilog.vl_types.all;
entity decoder is
port(
\in\ : in vl_logic_vector(31 downto 0);
sel : in vl_logic;
o0
www.eeworm.com/read/468753/6987293
voptfnk2rw
library verilog;
use verilog.vl_types.all;
entity mux24 is
port(
i0 : in vl_logic_vector(3 downto 0);
i1 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/468753/6987295
voptdyskse
library verilog;
use verilog.vl_types.all;
entity mux8 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987301
vopt20e0kz
library verilog;
use verilog.vl_types.all;
entity mux2 is
port(
i0 : in vl_logic_vector(31 downto 0);
i1 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987339
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity MemoryInterface is
port(
D : inout vl_logic_vector(31 downto 0);
A : in vl_logic_vector(31 downto
www.eeworm.com/read/468753/6987342
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sum5 is
port(
s : out vl_logic_vector(4 downto 0);
p : in vl_logic_vector(4 downto 0);