_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity MemoryInterface is
    port(
        D               : inout  vl_logic_vector(31 downto 0);
        A               : in     vl_logic_vector(31 downto 0);
        nMREQ           : in     vl_logic;
        nRW             : in     vl_logic;
        MAS             : in     vl_logic_vector(1 downto 0);
        nWAIT           : out    vl_logic;
        sysclk          : in     vl_logic;
        nRESET          : in     vl_logic
    );
end MemoryInterface;