代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/387416/8685271
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/286614/8755347
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
www.eeworm.com/read/286614/8755369
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity serial is
generic(
STATE_IDLE : string := "s0";
STATE1 : string := "s1";
STATE2 : string := "s2"
www.eeworm.com/read/385840/8786983
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
www.eeworm.com/read/384256/8886184
hif ibelieve.hif
Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
38
2267
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
www.eeworm.com/read/383505/8941193
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity booth16 is
generic(
width : integer := 16
);
port(
clk : in vl_logic;
reset :
www.eeworm.com/read/185603/9025786
qsf test.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/377687/9264663
v case3s.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3s.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
www.eeworm.com/read/377687/9264686
v case3s.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3s.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
www.eeworm.com/read/377687/9264700
v lfsr.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**************************************************