_primary.vhd

运用FPGA控制AD9957的操作

library verilog;
use verilog.vl_types.all;
entity serial is
    generic(
        STATE_IDLE      : string  := "s0";
        STATE1          : string  := "s1";
        STATE2          : string  := "s2";
        STATE3          : string  := "s3";
        STATE4          : string  := "s4";
        STATE5          : string  := "s5";
        STATE6          : string  := "s6";
        STATE7          : string  := "s7";
        STATE8          : string  := "s8";
        STATE9          : string  := "s9";
        STATE10         : string  := "s10";
        STATE11         : string  := "end"
    );
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        start           : in     vl_logic;
        len_reg         : in     vl_logic_vector(6 downto 0);
        addr            : in     vl_logic_vector(7 downto 0);
        din             : in     vl_logic_vector(63 downto 0);
        ncs             : out    vl_logic;
        sclk            : out    vl_logic;
        ser_in          : in     vl_logic;
        ser_out         : out    vl_logic;
        sd_io           : out    vl_logic;
        dout            : out    vl_logic_vector(63 downto 0);
        end_serial      : out    vl_logic
    );
end serial;