代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/154098/5642243
srd top.srd
f "noname"; #file 0
f "j:\example-8-1\modular_design\syn_top\virtex2.v"; #file 1
f "j:\example-8-1\modular_design\syn_top\top.v"; #file 2
VNAME 'work.module_c.verilog'; # view id 0
VNAME 'work.mod
www.eeworm.com/read/154076/5643133
crp coregen.crp
NEWPROJECT j:\projects\ise\arch_wzd_demo
SETPROJECT j:\projects\ise\arch_wzd_demo
SET BusFormat = BusFormatAngleBracket
SET XilinxFamily = Virtex2P
SET FlowVendor = Foundation_iSE
SET DesignFlow
www.eeworm.com/read/198746/6786438
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mvbc3tbw is
end mvbc3tbw;
www.eeworm.com/read/473809/6841718
qsf fpga_pro.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/294637/8214585
zsf wed.zsf
E:/电子设计竞赛/verilog/62256接口/db/62256.sim.vwf 0 1250000 445 1250000 0
E:/电子设计竞赛/verilog/62256接口/62256.vwf 0 2500000 612 2500000 0
E:/电子设计竞赛/verilog/62256接口/Waveform1.vwf 0 1000000 799 1000000 4
62256.
www.eeworm.com/read/173063/9676458
qsf cfb_sp.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/172784/9690237
log realpow_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
realpow_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 27, 1998 19:52:24
Verilog_XL_Turbo_NT 2.6.9 Nov 27, 19
www.eeworm.com/read/172784/9690247
log read_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 28, 1998 00:53:09
Verilog_XL_Turbo_NT 2.6.9 Nov 28
www.eeworm.com/read/172784/9690267
log read_timeval_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_timeval_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 27, 1998 10:14:53
Verilog_XL_Turbo_NT 2.6.9 Nov 2
www.eeworm.com/read/172784/9690279
log read_attribute_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_attribute_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 27, 1998 23:28:26
Verilog_XL_Turbo_NT 2.6.9 Nov