代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585981
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams64 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :
www.eeworm.com/read/159314/5585982
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams32 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :
www.eeworm.com/read/159314/5585983
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor5 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5585984
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor16 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5585989
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_srl16e is
generic(
init : integer := 0
);
port(
q : out vl_logic;
a0 :
www.eeworm.com/read/159314/5585996
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor3 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5586004
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams16 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :
www.eeworm.com/read/159314/5586006
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor8 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5586017
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor7 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5586021
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor6 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;