代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585543
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4 is
generic(
cds_action : string := "ignore"
);
port(
cout : out vl_logic;
cout0
www.eeworm.com/read/159314/5585544
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585545
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srl16 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585550
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldpe is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585551
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585554
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fde is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : o
www.eeworm.com/read/159314/5585557
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srlc16 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585558
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585567
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram64x1d is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo
www.eeworm.com/read/159314/5585576
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or5b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0