代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585503
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity omux2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
d0
www.eeworm.com/read/159314/5585508
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdr_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585520
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity xor3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585525
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585526
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x1d is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo
www.eeworm.com/read/159314/5585527
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildxi_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585528
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldcp_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585532
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufn_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
www.eeworm.com/read/159314/5585535
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity xnor4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585541
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :