_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity omux2 is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        o               : out    vl_logic;
        d0              : in     vl_logic;
        d1              : in     vl_logic;
        s0              : in     vl_logic
    );
end omux2;