代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/405978/11452019
sft freq2_2.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {freq2_2.vo freq2_2_v.sdo}}
}
www.eeworm.com/read/400225/11580369
log stdout.log
Starting: C:\pasic\synplcty\bin\mbin\synplify.exe
Version: 7.0.2
Date: Fri Sep 13 17:34:10 2002
Running synthesis on demo_amba:Synthesis_and_SpDE_files
log file: "\\Judd_ql_dallas
www.eeworm.com/read/262354/11590898
tcl create_wtut_ver.tcl
# Tcl script to run in the Xilinx Tcl shell or the ISE Tcl Console
# To run this script, type "source create_vtut_ver.tcl"
# at Tcl prompt.
# set up the project
project new wtut_ver.ise
pr
www.eeworm.com/read/347114/11690391
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
Iz]gBl1MVeY1@Aca5DC9B23
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/apex20ke_atoms.v)
L0 1618
OV;L
www.eeworm.com/read/347114/11690403
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffe_io is
port(
\Q\ : out vl_logic;
\CLK\ : in vl_logic;
\ENA\ : in vl_logic;
www.eeworm.com/read/347114/11690513
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11690634
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
IbX`i3
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratix_atoms.v)
L0 222
OV;L;5
www.eeworm.com/read/347114/11690777
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11690802
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/347114/11690861
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
valt3pram
ITQezdiY7oBT6M>5