代码搜索：verilog hdl 是什么？
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www.eeworm.com/read/368825/9676369
txt note.txt
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本程序只供交流学习之用
作者：woailiushui
2006/05/12
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编译环境：quartus2 4.0
语言：Verilog
可直接使用，完成对输入信号的整数，半整数分频
(0.5 和 1 没做 ^_^)
www.eeworm.com/read/172784/9690196
v port_info_test.v
/**********************************************************************
* $port_info example -- C source code using VPI PLI routines
*
* For the book, "The Verilog PLI Handbook", Chapter 5
* C
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v port_info_test.v
/**********************************************************************
* $port_info example -- Verilog test bench source code
*
* Verilog test bench to test the $port_info PLI application.
*
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v my_monitor_test.v
/**********************************************************************
* $my_monitor example -- Verilog test bench source code
*
* Verilog test bench to test the $my_monitor PLI application on
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log hello_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
hello_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 11:22:44
Verilog_XL_Turbo_NT 2.6.9 Nov 24, 1998
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log my_monitor1_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
my_monitor1_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 26, 1998 03:15:05
Verilog_XL_Turbo_NT 2.6.9 Dec 26
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log my_monitor2_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
my_monitor2_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Feb 10, 1999 13:16:34
Verilog_XL_Turbo_NT 2.6.9 Feb 10
www.eeworm.com/read/172784/9690476
v list_nets_test.v
/**********************************************************************
* $list_nets example -- Verilog test bench source code
*
* Verilog test bench to test the $list_nets PLI application.
*
www.eeworm.com/read/172784/9690614
log realpow_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
realpow_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 25, 1998 21:05:09
Verilog_XL_Turbo_NT 2.6.9 Dec 25, 19
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log pow_test.log
Host command: verilog.exe
Command arguments:
+cuzco_gui
pow_test.v
+gui
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 21:52:47
Verilog_XL_Turbo_NT 2.6.9 Nov 24, 1998